Dithered M by N clock dividers

A fractional clock divider comprising:

• a cyclic shift register to store a seed pattern, the seed pattern comprising M ones and N minus M zeros;
• a selector logic circuit having inputs to receive each bit of the cyclic shift register and a selector signal indicating which input from the cyclic shift register to output, the selector logic circuit also having an output to provide a clock enable sequence;
• a clock gate having inputs to receive an input clock signal and the clock enable sequence, the clock gate also having an output to provide a divided clock signal;
• a modulo N counter having an input to receive the input clock signal, the modulo N counter also having an output;
• a comparator having an input to receive the modulo N counter output, the comparator also having an output, wherein over N input clock cycles, the comparator is to output a value of one for one input clock cycle and a value of zero for a remainder of the N clock cycles;
• and
• a random number generator having an input to receive the comparator output, the random number generator having an output to provide the selector signal, wherein the random number generator is to output a number between zero and N minus one.