Filterless digital phase-locked loop

A sample rate converter (SRC) to re-clock an external signal to a local clock, comprising:

• an input port configured to receive input data from a first clock having a first clock rate;
• signal conditioning circuitry configured to operate from a second clock having a second clock rate;
• and
• a phase-locked loop (PLL), comprising:
• a frequency detector having an input port to receive the first clock and a feedback port to receive the second clock, the frequency detector comprising means to measure a frequency difference between the first clock rate and the second clock rate directly in the frequency dimension, and to drive an impulse signal, wherein the impulse signal is positive (“up”) when the frequency difference is positive and negative (“down”) when the frequency difference is negative;
• and
• a number-controlled oscillator (NCO) configured to adjust a second clock frequency responsive to the impulse signal, wherein an output of the NCO provides the second clock.

An audio device, comprising:

• an audio input to receive audio data at a first clock rate;
• an audio processor circuit to provide processed audio data, the audio processor circuit comprising signal conditioning circuitry to operate at a second clock rate, and a phase-locked loop (PLL), comprising:
• a frequency detector configured to measure frequency directly in a frequency dimension without respect to phase, having a first input to sample the first clock rate and a feedback input to sample the second clock rate, the frequency detector comprising circuitry, including an integrator, to measure a frequency difference between the first clock rate and the second clock rate and to drive an impulse signal, wherein the impulse signal is positive when the frequency difference is positive and negative when the frequency difference is negative;
• and
• a number-controlled oscillator (NCO) to adjust a second clock frequency responsive to the impulse signal, wherein an output of the NCO operates at the second clock rate, wherein the integrator of the frequency detector has an enable input that enables on a signal from one of the NCO or the first input;
• and
• a driver to drive the processed audio data.