US 10,651,856 B2Granted

Four-phase oscillator and CDR circuit

AssigneeFujitsu Limited

InventorTakashi Shiraishi

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Abstract

A four-phase oscillator includes, a first oscillator configured to output a first differential signal, a second oscillator configured to output a second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, and a control circuit. The first oscillator includes a first tail current source and a second tail current source. The second oscillator includes a third tail current source and a fourth tail current source. The control circuit changes the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source.

Claims9

Dependent claims

A clock and data recovery circuit comprising:

a first oscillator configured to output a first differential signal, the first oscillator including
a first resonator including an inductor and a capacitor coupled in parallel,
a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,
a first tail current source coupled to the first pair of transistors,
first input differential pair transistors configured to receive a second differential signal, and
a second tail current source coupled to the first input differential pair transistors;
a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including
a second resonator including an inductor and a capacitor coupled in parallel,
a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,
a third tail current source coupled to the second pair of transistors,
second input differential pair transistors configured to receive the first differential signal, and
a fourth tail current source coupled to the second input differential pair transistors;
a control circuit configured to control, based on which of a first resonant frequency at which the first resonator resonates and a second resonant frequency at which the second resonator resonates is higher, at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source;
an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;
a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;
a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;
a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;
a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal;
and
a data generation circuit configured to regenerate data from the received data according to the first differential signal.

17 more elements

A clock and data recovery circuit comprising:

a first oscillator configured to output a first differential signal, the first oscillator including
a first resonator including an inductor and a capacitor coupled in parallel,
a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,
a first tail current source coupled to the first pair of transistors,
first input differential pair transistors configured to receive a second differential signal, and
a second tail current source coupled to the first input differential pair transistors;
a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including
a second resonator including an inductor and a capacitor coupled in parallel,
a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,
a third tail current source coupled to the second pair of transistors,
second input differential pair transistors configured to receive the first differential signal, and
a fourth tail current source coupled to the second input differential pair transistors;
a control circuit configured to control, based on a first resonant frequency at which the first resonator resonates and a second resonant frequency at which the second resonator resonates, at least one of a difference between a first current value supplied from the first tail current source and a second current value supplied from the second tail current source and a difference between a third current value supplied from the third tail current source and a fourth current value supplied from the fourth tail current source;
an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;
a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;
a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;
a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;
a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal;
and
a data generation circuit configured to regenerate data from the received data according to the first differential signal.

17 more elements

A clock and data recovery circuit comprising:

a four-phase oscillator configured to output a first differential signal and a second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the four-phase oscillator including
a first oscillator configured to output a first differential signal, the first oscillator including
a first resonator including an inductor and a capacitor coupled in parallel,
a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,
a first tail current source coupled to the first pair of transistors,
first input differential pair transistors configured to receive a second differential signal, and
a second tail current source coupled to the first input differential pair transistors;
a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including
a second resonator including an inductor and a capacitor coupled in parallel,
a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,
a third tail current source coupled to the second pair of transistors,
second input differential pair transistors configured to receive the first differential signal, and
a fourth tail current source coupled to the second input differential pair transistors;
and
a control circuit configured to change the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source
an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;
a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;
a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;
a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;
a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal;
a data generation circuit configured to regenerate data from the received data according to the first differential signal.

18 more elements

A clock and data recovery circuit comprising:

a four-phase oscillator configured to output a first differential signal and a second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the four-phase oscillator including
a first oscillator configured to output a first differential signal, the first oscillator including
a first resonator including an inductor and a capacitor coupled in parallel,
a first cross-coupled circuit in which a first pair of transistors coupled to the first resonator are cross-coupled,
a first tail current source coupled to the first pair of transistors,
first input differential pair transistors configured to receive a second differential signal, and
a second tail current source coupled to the first input differential pair transistors;
a second oscillator configured to output the second differential signal shifted in phase with respect to the first differential signal by 90 or −90 degrees, the second oscillator including
a second resonator including an inductor and a capacitor coupled in parallel,
a second cross-coupled circuit in which a second pair of transistors coupled to the second resonator are cross-coupled,
a third tail current source coupled to the second pair of transistors,
second input differential pair transistors configured to receive the first differential signal, and
a fourth tail current source coupled to the second input differential pair transistors, and
a control circuit configured to change the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a second current value supplied from the second tail current source and a difference between a third current value supplied from the third tail current source and a fourth current value supplied from the fourth tail current source;
an inverter configured to output a third differential signal inverted the phase of the second differential signal based on the change of the frequency by the control circuit;
a first phase detect circuit configured to output a first phase detect signal based on a difference between a received data signal and the first differential signal;
a second phase detect circuit configured to output a second phase detect signal based on a difference between a received data signal and the second differential signal;
a frequency detect circuit configured to compare the first phase detect signal with the second phase detect signal, and output a frequency detect signal based on a difference between the received signal and the first differential signal;
a control voltage generation circuit configured to generate a control voltage to adjust frequencies and phases of the first differential signal and the second differential signal based on the first phase detect signal and the frequency detect signal;
a data generation circuit configured to regenerate data from the received data according to the first differential signal.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/992,245Filed 30 May 2018
Priority: JP 2017-1094771 Jun 2017
Published: US 2018/0351559 A16 Dec 2018
Granted: 12 May 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H03L 7/0807
Details of the phase-locked loop: concerning mainly a recovery circuit for the reference signal
H03B 5/1215
The amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a…
H03B 5/1225
Using multiple transistors for amplification: the generator comprising multiple amplifiers connected in parallel
H03B 5/1228
Active element in amplifier being semiconductor device: the amplifier comprising one or more field effect transistors