Timing insulation circuitry for partial reconfiguration of programmable integrated circuits

A method, comprising:

• providing a platform implemented in programmable circuitry of a device, wherein the platform includes a static platform circuitry having a bus endpoint and a platform partial reconfiguration region including a direct memory access (DMA) engine coupled to the bus endpoint, an interconnect coupled to the DMA engine, and a memory controller coupled to the DMA engine, wherein the platform partial reconfiguration region is configured to connect user-specified circuitry with the bus endpoint and an off-chip memory local to the device and distinct from a memory of a host data processing system;
• providing a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform, wherein the first partial reconfiguration region is reserved for implementing the user-specified circuitry;
• providing timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform partial reconfiguration region of the platform and the first partial reconfiguration region;
• and
• implementing a modified version of the platform circuitry in the device while keeping the timing insulation circuitry unchanged;
• and
• wherein the bus endpoint is configured to maintain a communication link with the host data processing system while the first partial reconfiguration region or the platform partial reconfiguration region or both the first partial reconfiguration region and the platform partial reconfiguration region are reconfigured.