Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library

A method of configuring a low power integrated circuit (IC) using a flip-flop, the method comprising:

• receiving, by a master latch, a clock signal, a complimentary clock signal, a data signal, and a complimentary data signal, wherein the complimentary clock signal is produced by a clock inverter of the flip-flop and the complimentary data signal is produced by a data inverter of the flip-flop;
• generating, by the master latch, when the clock signal is at a low logic level, a first master internal signal at a first node of the master latch and a second master internal signal at a second node of the master latch based on the clock signal, the complimentary clock signal, the data signal, and the complimentary data signal, the first master internal signal being complimentary to the second master internal signal;
• and
• electrically connecting a third node and a fourth node through an NMOS transistor when the clock signal is at a high logic level,
• wherein the first node and the second node are shorted for supplying power to the flip-flop when the clock signal is at the high logic level.

A flip-flop for a low power integrated circuit (IC), the flip-flop comprising:

• an input data inverter;
• and
• a master latch configured to:
• receive a clock signal, a data signal, and a complimentary data signal that is produced by the input data inverter;
• generate a first master internal signal at a first node of the master latch and a second master internal signal at a second node of the master latch based on the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level, the first master internal signal being complimentary to the second master internal signal;
• and
• electrically connect a third node and a fourth node when the clock signal is at a high logic level,
• wherein the first node and the second node are shorted for supplying power to the flip-flop when the clock signal is at the high logic level.