Transaction-based on-die termination
AssigneeRambus Inc.
InventorsKyung Suk Oh, Ian P. Shaeffer
Life of this patent
Estimating the term…
Abstract
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
Claims21
A memory component comprising:
- a memory core;
- a control interface to receive commands and a select signal, the select signal indicating, for each of the commands, whether the memory component is a target of an operation specified by the command;
- a data input/output (I/O);
- and
- termination circuitry to:
- terminate the data I/O with a first termination impedance in response to reception, via the control interface, of (i) a first command specifying a memory write operation and (ii) the select signal in a state indicating that the memory component is a target of the memory write operation;
- terminate the data I/O with a second termination impedance after reception, via the data I/O, of write data to be stored within the memory core per the memory write operation;
- and
- disable termination of the data I/O in response to reception, via the control interface, of (i) a second command indicating a memory read operation and (ii) the select signal in a state indicating that the memory component is a target of the memory read operation.
A method of operation within a memory component having a memory core, the method comprising:
- terminating a data input/output (I/O) with a first termination impedance in response to concurrent reception of a first command specifying a memory write operation and a select signal in a state indicating that the memory component is a target of the memory write operation;
- terminating the data I/O with a second termination impedance after reception, via the data I/O, of write data to be stored within the memory core per the memory write operation;
- and
- disabling termination of the data I/O in response to concurrent reception of a second command indicating a memory read operation and the select signal in a state indicating that the memory component is a target of the memory read operation.
A dynamic random access memory integrated circuit (DRAM IC) comprising:
- a control interface to receive commands and a select signal, the select signal indicating, for each of the commands, whether the DRAM IC is a target of an operation specified by the command;
- a data input/output (I/O);
- and
- termination circuitry to:
- terminate the data I/O with a first termination impedance in response to reception, via the control interface, of (i) a first command specifying a memory write operation and (ii) the select signal in a state indicating that the memory component is a target of the memory write operation;
- terminate the data I/O with a second termination impedance a predetermined time after reception of the first command;
- disable termination of the data I/O in response to reception, via the control interface, of (i) a second command indicating a memory read operation and (ii) the select signal in a state indicating that the memory component is a target of the memory read operation;
- and
- terminate the data I/O with the second termination impedance in response to detection of a third command at the control interface in conjunction with the select signal in a state indicating that the memory component is not a target of an operation specified by the third command.
Dependencies are inferred from the claim text.