Multiple chip synchronization via single pin monitoring of an external timing capacitor

A system comprising:

• a circuit board;
• a first external capacitor mounted on the circuit board;
• a first integrated circuit mounted on the circuit board, the first integrated circuit including:
• a first pin coupled to the first external capacitor, a first voltage input providing a first voltage, and a second voltage input providing a second voltage;
• a first transistor coupled between the first pin and the first voltage input and having a control input;
• a second transistor coupled between the first pin and the second voltage input and having a control input;
• and
• a first monitor and driving circuit having an input coupled to the first pin, having an output coupled to the control input of the first transistor, having an output coupled to the control input of the second transistor, and having a first response output, the first monitor and driving circuit monitoring the first pin for:
• a first threshold voltage between the first voltage and the second voltage, the second voltage, and a first response voltage between the first threshold voltage and the first voltage;
• a second integrated circuit mounted on the circuit board the second integrated circuit including:
• a second pin coupled to the first external capacitor, a third voltage input providing a third voltage, and a fourth voltage input providing a fourth voltage;
• a third transistor coupled between the second pin and the third voltage input and having a control input;
• a fourth transistor coupled between the first pin and the fourth voltage input and having a control input;
• and
• a second monitor and driving circuit having an input coupled to the second pin, having an output coupled to the control input of the third transistor, having an output coupled to the control input of the fourth transistor, and having a second response output, the second monitor and driving circuit monitoring the second pin for:
• a second threshold voltage between the third voltage and the fourth voltage, the fourth voltage, and a second response voltage between the second threshold voltage and the third voltage.

A method of operating an integrated circuit comprising:

• charging a capacitor from a first voltage to a second voltage;
• enabling detection of a response voltage upon a voltage on the capacitor passing through a first threshold voltage between the first voltage and the second voltage;
• coupling the capacitor to the first voltage upon the voltage on the capacitor reaching the second voltage;
• producing a response in the integrated circuit upon the voltage on the capacitor passing through the response voltage, which is between the first threshold voltage and the first voltage.