Level shifter

A level shifting method, comprising:

• receiving an enable signal having a logic high state and a logic low state in a first voltage domain;
• equalizing output signals at first and second output terminals in response to the logic low state of the enable signal;
• receiving an input signal in the first voltage domain on an input terminal;
• outputting complementary first and second output signals in a second voltage domain higher than the first voltage domain at the first and second output terminals based on the input signal and the logic high state of the enable signal.

A level shifting system, comprising:

• an input terminal configured to receive an input signal in a first voltage domain;
• a first clock terminal configured to receive a first clock signal having a logic low state and a logic high state in the first voltage domain;
• a level shifter coupled to the input terminal and configured to equalize first and second output signals in response to the logic low state of the first clock signal, and to output an output signal in a second voltage domain higher than the first voltage domain in response to the input signal and the logic high state of the clock signal;
• a latch circuit having a second clock terminal configured to receive a second clock signal, the latch circuit configured to latch the output signal from the level shifter in the second voltage domain in response to the second clock signal, wherein the second clock signal and the first clock signal are in phase with one another.