Signal receiver circuit

A signal receiver circuit, comprising:

• a negative voltage applier suitable for applying a negative voltage or a ground voltage to a common source node in response to a first clock;
• a first sampling NMOS transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal;
• a second sampling NMOS transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal;
• an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock;
• a first precharge PMOS transistor having a gate receiving a second clock, a source coupled to a pull-up voltage terminal, and a drain coupled to a first output node;
• a second precharge PMOS transistor having a gate receiving the second clock, a source coupled to the pull-up voltage terminal, and a drain coupled to a second output node;
• a first blocking NMOS transistor having a gate receiving the second clock, a source coupled to the first sampling node, and a drain coupled to the second output node;
• and
• a second blocking NMOS transistor having a gate receiving the second clock, a source coupled to the second sampling node, and a drain coupled to the first output node;
• and
• an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock,
• wherein the second clock is an inverted and delayed clock of the first clock, and
• wherein:
• during a first period in which the first clock is at the second logic level and the second clock is at the first logic level, the first and second output nodes are precharged, and the first and second sampling nodes are equalized;
• during a second period in which the first and second clocks are at the first logic level, the first and second input signals are sampled as the negative voltage is applied to the common source node to reflect the sampled result into the first and second sampling nodes;
• and
• during a third period in which the first clock is at the first logic level and the second clock is at the second logic level, the first and second output nodes are coupled to the first and second sampling nodes, respectively, and the voltage difference between the first and second output nodes is amplified.