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US 10,651,812 B2Granted
Cascode amplifier having feedback circuits
AssigneeSkyworks Solutions, Inc.
InventorsAmbarish Roy, Eric Marsan, Stephen Richard Moreschi
Life of this patent
Estimating the term…
Abstract
Cascode amplifier having feedback circuits. In some embodiments, an amplifier can include a first transistor and a second transistor arranged in a cascode configuration, with each transistor having a gate. The amplifier can further include a first feedback circuit implemented between an output of the second transistor and the gate of the second transistor. The amplifier can further include a second feedback circuit implemented between the output of the second transistor and the gate of the first transistor.
Claims21
An amplifier comprising:
- first and second transistors arranged in a cascode configuration, each transistor having an input node, an output node, and a common node;
- a first feedback circuit implemented between the output node of the second transistor and the common node of the second transistor, the first feedback circuit including a first parallel combination and a second parallel combination connected in series, the first parallel combination including a first resistance parallel with a series combination of a second resistance and a first capacitance, the second parallel combination including a third resistance parallel with a second capacitance;
- and
- a second feedback circuit implemented between the output node of the second transistor and the input node of the first transistor.
1 more element
An amplifier comprising:
- a first transistor and a second transistor arranged in a cascode configuration, each transistor having an input node, an output node, and a common node;
- a first feedback circuit configured to provide gain control of the second transistor, and implemented between the output node of the second transistor and the common node of the second transistor, the first feedback circuit including a first parallel combination and a second parallel combination connected in series, the first parallel combination including a first resistance parallel with a series combination of a second resistance and a first capacitance, the second parallel combination including a third resistance parallel with a second capacitance;
- a second feedback circuit configured to provide an increase in a desired frequency range of the amplifier, and implemented between the output node of the second transistor and the input node of the first transistor;
- and
- a passive element implemented between the first transistor and the second transistor, and configured to compensate for an effect of the second feedback circuit.
2 more elements
A semiconductor die comprising:
- a semiconductor substrate;
- and
- an amplifier circuit implemented on the semiconductor substrate and including first and second transistors arranged in a cascode configuration, each transistor having an input node, an output node, and a common node;
- a first feedback circuit implemented between the output node of the second transistor and the common node of the second transistor, the first feedback circuit including a first parallel combination and a second parallel combination connected in series, the first parallel combination including a first resistance parallel with a series combination of a second resistance and a first capacitance, the second parallel combination including a third resistance parallel with a second capacitance;
- and a second feedback circuit implemented between the output node of the second transistor and the input node of the first transistor.
2 more elements
A wireless device comprising:
- a transceiver configured to process a signal;
- an antenna in communication with the transceiver and configured to facilitate the signal associated with the transceiver;
- and
- an amplifier circuit provided between the transceiver and the antenna and configured to provide amplification for the signal, the amplifier circuit including first and second transistors arranged in a cascode configuration, each transistor having an input node, an output node, and a common node;
- a first feedback circuit implemented between the output node of the second transistor and the common node of the second transistor, the first feedback circuit including a first parallel combination and a second parallel combination connected in series, the first parallel combination including a first resistance parallel with a series combination of a second resistance and a first capacitance, the second parallel combination including a third resistance parallel with a second capacitance;
- and a second feedback circuit implemented between the output node of the second transistor and the input node of the first transistor.
3 more elements
Dependencies are inferred from the claim text.