Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage with reduced capacitor mismatch sensitivity

An electronic system comprising:

• a switched-capacitor gain stage circuit comprising an input node (Vin), an output node (Vo), a central node, and an operational amplifier comprising a first amplifier input, a second amplifier input, and an amplifier output, where the operational amplifier is connected in a non-flip-around configuration wherein the amplifier output is connected over a feedback capacitor to a central node during a gain phase;
• a first capacitor (C1) that selectively couples the central node to the input node during a sampling phase and that is selectively coupled over the central node to the first amplifier input during the gain phase;
• one or more reference loading circuits connecting a first reference voltage (Vrefp) and a second reference voltage (Vrefm) to the common node, each reference loading circuit comprising:
• a second capacitor (C3) that selectively couples the first reference voltage (Vrefp) to the central node to pre-charge the second capacitor with the first reference voltage during the sampling phase, and that selectively couples the first reference voltage and/or the second reference voltage over the central node to the first amplifier input during the gain phase;
• a third capacitor (C4) that selectively couples the second reference voltage (Vrefm) to the central node to pre-charge the third capacitor with the second reference voltage during the sampling phase, and that selectively couples the first reference voltage and/or second reference voltage over the central node to the first amplifier input during the gain phase;
• and
• a switching configuration including multiple switches that are controllable to connect the first capacitor between the input node and the central node during the sampling phase while simultaneously connecting a common-mode voltage over the feedback capacitor to the central node while also connecting the amplifier output to the first amplifier input, and to connect the amplifier output in feedback over the feedback capacitor to the central node during the gain phase while simultaneously connecting the central node to the first amplifier input and disconnecting the input node from the first and second capacitors during the gain phase.

A method for applying a gain to an input signal, the method performed in a switched-capacitor gain stage circuit including an input node, an output node, a plurality of sampling capacitors, and an operational amplifier connected in a non-flip-around configuration including a first amplifier input, a second amplifier input, and an amplifier output, the method comprising the steps of:

• first configuring multiple switches of the switched-capacitor gain stage circuit in a first configuration where an input sampling switched capacitor selectively couples the input node to a central node which is in turn coupled to a common-mode reference voltage (Vcm) during a sampling phase, where both terminals of a feedback sampling switched capacitor are selectively coupled to the common mode reference voltage via the central node during the sampling phase, and where a reference loading circuit selectively couples first and second first references to pre-charge first and second sampling switched capacitors during the sampling phase;
• and
• second configuring multiple switches of the switched-capacitor gain stage circuit in a second configuration where the input sampling switched capacitor selectively couples the common mode reference voltage to the first amplifier input during the gain phase, where the feedback sampling switched capacitor selectively couples the amplifier output to the central node during the gain phase, and where the reference loading circuit selectively couples each of the first and second reference voltages over at least one of the first and second sampling switched capacitors to the first amplifier input during the gain phase.