Accurate peak detection architecture for secondary controlled AC-DC converter

A AC-Dc converter comprising:

• a transformer including a primary side coupled to receive a sinusoidal input and a power switch (PS) coupled between the sinusoidal input and the transformer, and a secondary side having a DC output and a synchronous rectifier (SR) coupled between the DC output and the transformer;
• and
• a secondary side controller comprising an integrated circuit (IC) including a peak-detector (PKD) module, and a single SR sense (SR-SNS) pin through which the IC is coupled to a drain of the SR to sense voltage thereon, the PKD module comprising:
• a comparator with a signal input coupled through a sensing capacitor to the single SR-SNS pin, a reference input coupled to signal ground, and an output to output a peak voltage detection signal (PKD_OUT);
• and
• a clamping circuit including:
• a closed loop operational amplifier (OPAMP) having a first input coupled through the sensing capacitor to the single SR-SNS pin, a second input coupled to a reference voltage (VREF), and an output (opamp_out);
• a transistor having a control terminal coupled to the output of the OPAMP, a first terminal coupled to the first input of the OPAMP and through the sensing capacitor to the single SR-SNS pin, a second terminal coupled to the reference input of the peak comparator and to signal ground;
• and
• a rectifying element coupled between the signal input and the reference input of the peak comparator.

A method of operating a secondary side controller for a AC-DC converter, the method comprising:

• coupling a sinusoidal signal from a drain of a synchronous rectifier (SR) on a secondary side of the AC-DC converter to a peak-detector (PKD) module in the secondary side controller;
• clamping the sinusoidal signal to maximum positive and negative voltages to generate an input signal (VSIG);
• sampling the input signal and holding a peak voltage of the input signal on a sample and hold (S/H) capacitor;
• subtracting a DC offset voltage from the peak voltage held on the S/H capacitor to generate a reference voltage (VREF);
• coupling the input signal to a signal input of a peak comparator and coupling the reference voltage to a reference input of the peak comparator;
• and
• comparing the input signal to the reference voltage, and when the input signal goes below the reference voltage outputting from the peak comparator to a primary side controller a peak voltage detection signal (PKD_OUT).