Down-mode valley-current-sense replica linearization

An integrated circuit (IC) chip, the DC/DC boost convcrtcr comprising:

• a first pin, a second pin and a third pin;
• a low-side power transistor and a high-side power transistor coupled in series between the first pin and the second pin, the high-side power transistor having a first body contact;
• a switch-node between the low-side power transistor and the high-side power transistor, the switch node being coupled to the third pin;
• a back-gate disconnect transistor coupled between the first body contact of the high-side power transistor and the second pin;
• a valley-current sensing circuit including:
• a comparator having an inverting input, a non-inverting input, and an output,
• a first replica transistor that is coupled in series with a first current sink between the switch-node and a lower rail, the first replica transistor having a second body contact,
• a first node between the first replica transistor and the first current sink, the first node being coupled to the inverting input of the comparator, and
• a second replica transistor that is coupled in series with a second current sink between a max reference voltage input and the lower rail,
• a second node between the second replica transistor and the second current sink, the second node being coupled to the non-inverting input of the comparator;
• and
• a current measurement linearization circuit including:
• a back-gate sensing transistor that is coupled between the first body contact and the second body contact of the first replica transistor, and
• a back-gate reset transistor that is coupled between the second body contact and the max reference voltage input.

A method of operating a DC/DC boost converter, the converter including:

• a low-side power transistor and a high-side power transistor coupled in series between a first pin and a second pin, the high-side power transistor having a first body contact,
• a switch-node between the low-side power transistor and the high-side power transistor, the switch node being coupled to a third pin,
• a first replica transistor coupled between the switch node and a first current source, the first replica transistor having a second body contact
• a second replica transistor coupled between a max voltage input and a second current source, the method comprising:
• during a boost-mode connecting the first body contact of the high-side power transistor and the second body contact of the first replica transistor together and
• during a down-mode when the low-side power transistor is off connecting the first body contact and the second body contact together and
• during the down-mode when the low-side power transistor is on disconnecting the first body contact and the second body contact and coupling the second body contact to a max reference voltage that is equal to a larger one of an input voltage and an output voltage.