Method for static gate clamping in multi-output gate driver systems

A method for operating a multi-output gate driver system including first and second gate drivers each including an output coupled to a power device, the method comprising:

• turning on the power device with the first gate driver output, sensing a voltage of the second gate driver output to determine that the voltage at the second gate driver output is greater than a first reference voltage, and clamping the voltage of the second gate driver output to a first clamping voltage in a first mode of operation;
• turning off the power device with the first gate driver output, sensing the voltage of the second gate driver output to determine that the voltage at the second gate driver output is less than a second reference voltage, and clamping the voltage of the second gate driver output to a second clamping voltage in a second mode of operation;
• sensing the second gate driver output with first and second comparators in the first mode of operation;
• sensing the second gate driver output with first and second comparators in the second mode of operation;
• and
• selectively placing the second driver in a high impedance state depending upon a logic state of the first and second comparators, and a logic state of an input signal of the multi-output gate driver system.

A method of operating a multi-output gate driver system comprising a power device having a gate node, the method comprising:

• actively switching the power device on and off with a first driver coupled to the gate node;
• selectively driving the gate node with a second driver;
• comparing an output of the second driver to a first reference voltage to generate a first logic signal;
• comparing the output of the second driver to a second reference voltage to generate a second logic signal;
• logically combining a control signal of the multi-output gate driver system, the first logic signal, and the second logic signal to generate an output logic signal;
• clamping the output of the second driver to either a positive voltage rail or a negative voltage rail in response to the output logic signal;
• and
• selectively placing the second driver in a high impedance state in response to the output logic signal.