US 10,651,373 B2 · Memory device and fabrication method thereof

Abstract

A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

Claims20

Dependent claims

A method for forming an integrated circuit, comprising:

forming a dielectric layer over a cell region and a logic region of a substrate;
forming a resistance switching layer over the dielectric layer;
and
performing at least one etch process to pattern the resistance switching layer into at least one resistance switching element in the cell region, wherein a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/194,124Filed 16 Nov 2018 · us provisional application

Priority

28 Sep 2018

Published

US 2020/0106007 A12 Apr 2020

Granted

12 May 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10N 50/01
Galvanomagnetic devices: manufacture or treatment
H10B 61/10
Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices: comprising components having two electrodes, e.g. diodes or MIM elements
H10B 61/22
Comprising components having three or more electrodes, e.g. transistors: of the field-effect transistor [FET] type
H10B 61/00
Magnetic memory devices

Memory device and fabrication method thereof

Life of this patent

Memory device and fabrication method thereof

Life of this patent

Abstract

Claims20