Synaptic semiconductor device and neural networks using the same

A synaptic semiconductor device, comprising:

• a channel/source stack structure vertically arranged in the order of a channel region and a source region from a semiconductor substrate;
• a floating gate and a control gate spaced apart from a sidewall of the channel/source stack structure interlaying with a gate insulating film on the semiconductor substrate;
• and
• a drain region formed in the semiconductor substrate adjacent to the control pate, wherein:
• the gate insulating film is also provided between the control gate and the semiconductor substrate,
• a drain extension having a conductivity type equal to that of the drain region is formed in the semiconductor substrate from the drain region to a lower portion of the channel/source stack structure,
• the floating gate is formed of a semiconductor material having a conductivity type opposite to that of the drain region and is a semi-floating gate having a protruding portion that contacts the drain extension by a PN junction,
• the channel/source stack structure is a columnar structure vertically stacked with the channel region and the source region on the semiconductor substrate, the channel region having a predetermined vertical length,
• the floating gate is a cylindrical shape surrounding the sidewall of the columnar channel/source structure interlaying with the gate insulating film, the protruding portion having a circularly protruding portion on a lower portion of the floating gate,
• the first and the second control gates are a ring shape respectively surrounding upper and lower portions of the cylindrical sidewall of the floating gate interlaying with the gate insulating film,
• the drain region is a ring shape surrounding the first and the second control gates, and
• the drain extension fills the interior of the ring shaped drain region in the semiconductor substrate and forms a PN junction with the circularly protruding portion of the floating gate.

A synaptic semiconductor device, comprising:

• a channel/source stack structure vertically arranged in the order of a channel region and a source region from a semiconductor substrate;
• a floating gate and a control gate spaced apart from a sidewall of the channel/source stack structure interlaying with a gate insulating film on the semiconductor substrate;
• and
• a drain region formed in the semiconductor substrate adjacent to the control gate, wherein:
• the gate insulating film is also provided between the control gate and the semiconductor substrate,
• a drain extension having a conductivity type equal to that of the drain region is formed in the semiconductor substrate from the drain region to a lower portion of the channel/source stack structure,
• the floating gate is formed of a semiconductor material having a conductivity type opposite to that of the drain region and is a semi-floating gate having a protruding portion that contacts the drain extension by a PN junction,
• the semiconductor substrate, the channel region and the source region are formed of crystalline silicon or polycrystalline silicon,
• the control gate is vertically divided into a first control gate and a second control gate interlaying with the gate insulating film on a sidewall of the floating gate,
• the channel/source stack structure is a columnar structure vertically stacked with the channel region and the source region on the semiconductor substrate, the channel region having a predetermined vertical length,
• the floating gate is a cylindrical shape surrounding the sidewall of the columnar channel/source structure interlaying with the gate insulating film, the protruding portion having a circularly protruding portion on a lower portion of the floating gate,
• the first and the second control gates are a ring shape respectively surrounding upper and lower portions of the cylindrical sidewall of the floating gate interlaying with the gate insulating film,
• the drain region is a ring shape surrounding the first and the second control gates, and
• the drain extension fills the interior of the ring shaped drain region in the semiconductor substrate and forms a PN junction with the circularly protruding portion of the floating gate.

A synaptic semiconductor device, comprising:

• a channel/source stack structure vertically arranged in the order of a channel region and a source region from a semiconductor substrate;
• a floating gate and a control gate spaced apart from a sidewall of the channel/source stack structure interlaying with a gate insulating film on the semiconductor substrate;
• and
• a drain region formed in the semiconductor substrate adjacent to the control pate, wherein:
• the gate insulating film is also provided between the control gate and the semiconductor substrate,
• a drain extension having a conductivity type equal to that of the drain region is formed in the semiconductor substrate from the drain region to a lower portion of the channel/source stack structure,
• the floating gate is formed of a semiconductor material having a conductivity type opposite to that of the drain region and is a semi-floating gate having a protruding portion that contacts the drain extension by a PN junction,
• at least one of the drain region and the drain extension is formed of silicon germanium or germanium,
• the control gate is vertically divided into a first control gate and a second control gate interlaying with the gate insulating film on a sidewall of the floating gate,
• the channel/source stack structure is a columnar structure vertically stacked with the channel region and the source region on the semiconductor substrate, the channel region having a predetermined vertical length,
• the floating gate is a cylindrical shape surrounding the sidewall of the columnar channel/source structure interlaying with the gate insulating film, the protruding portion having a circularly protruding portion on a lower portion of the floating gate,
• the first and the second control gates are a ring shape respectively surrounding upper and lower portions of the cylindrical sidewall of the floating gate interlaying with the gate insulating film,
• the drain region is a ring shape surrounding the first and the second control gates, and
• the drain extension fills the interior of the ring shaped drain region in the semiconductor substrate and forms a PN junction with the circularly protruding portion of the floating gate.