Three dimensional memory

An integrated circuit comprising:

• a conductive source line having a vertical thickness and consists of heavily doped tungsten silicide throughout the vertical thickness;
• a monolithic pillar of semiconductive material having a constant diameter throughout a height of the pillar with a lower surface physically contacting the source line material and extending upward from the source line in a substantially perpendicular direction, the pillar of semiconductive material having opposing vertical sidewalls and having a first portion that functions as a source and a second portion that functions as a drain, the monolithic pillar having a uniform composition and an absence of interfaces, seams and large defects throughout the height of the pillar;
• gate dielectric material along the opposing vertical sidewalls;
• a field effect transistor comprising a channel and control gate, the control gate being separated from the pillar of semiconductive material by the gate dielectric material, wherein the channel is formed in the pillar of semiconductive material, and the control gate is separated from the source line by an insulating material;
• and
• two or more memory cells stacked on the field effect transistor, the two or more memory cells comprising channels formed in the monolithic pillar of semiconductive material, the monolithic pillar extending upward from the source line through the two or more memory cells;
• wherein the tungsten silicide source line material has an etch rate no faster than 33% as fast as an etch rate of the insulating material.