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US 10,651,314 B2Granted
Nanowire stack GAA device with inner spacer and methods for producing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsI-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H. Diaz
Life of this patent
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Abstract
A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
Claims20
A device, comprising:
- a substrate;
- a stack of nanowire structures over the substrate, the stack of nanowire structures including a topmost nanowire structure and a lower nanowire structure stacked lower than the topmost nanowire with respect to the substrate, a length of the topmost nanowire structure being less than a length of the lower nanowire structure;
- a source/drain structure adjacent the topmost nanowire structure and wrapping around a first portion of the lower nanowire structure;
- a gate structure wrapping around the topmost nanowire structure and wrapping around a second portion of the lower nanowire structure;
- and
- an inner spacer structure laterally between the source/drain structure and the gate structure, the inner spacer structure including a first inner spacer segment adjacent to the topmost nanowire structure and a second inner spacer segment adjacent to the lower nanowire structure.
3 more elements
A device, comprising:
- a substrate;
- and
- a first transistor and a second transistor over the substrate, each of the first transistor and the second transistor including:
- a stack of nanowire structures over the substrate, the stack of nanowire structures including a topmost nanowire structure and a lower nanowire structure stacked lower than the topmost nanowire with respect to the substrate, a length of the topmost nanowire structure being less than a length of the lower nanowire structure;
- a source/drain structure adjacent the topmost nanowire structure and wrapping around a first portion of the lower nanowire structure;
- and
- a gate structure wrapping around the topmost nanowire structure and wrapping around a second portion of the lower nanowire structure;
- wherein the topmost nanowire structure of the first transistor is at a different level from the topmost nanowire structure of the second transistor.
5 more elements
A method, comprising:
- receiving a wafer, the wafer including a stack of epitaxy layers over a substrate, the stack of epitaxy layers including a plurality of semiconductor epitaxy layers and a plurality of sacrificial epitaxy layers stacked in an alternating sequence;
- forming a fin structure including a stack of strips orientated in a first direction by patterning the stack of epitaxy layers, the stack of strips including a plurality of semiconductor strips and a plurality of sacrificial strips;
- forming a gate structure over the fin structure;
- forming a receded semiconductor strip by removing portions of a topmost semiconductor strip of the semiconductor strips such that a length of the topmost semiconductor strip is shorter than a length of a bottommost semiconductor strip of the semiconductor strips;
- forming receded sacrificial strips by removing portions of the plurality of sacrificial strips, the receded sacrificial strips each including recessed edge surfaces;
- forming an inner spacer adjacent to the recessed edge surfaces of the receded sacrificial strips;
- and
- forming a source/drain structure adjacent to the inner spacer and the plurality of semiconductor strips.
5 more elements
Dependencies are inferred from the claim text.