Reduced transistor resistance using doped layer

An apparatus comprising:

• a substrate;
• a first layer including a doped first material that includes at least one of a group III-V material, a group IV material, or combinations thereof;
• a second layer including a second material that includes at least one of a group III-V material, a group IV material, or combinations thereof;
• a third layer including a doped third material that includes at least one of a group III-V material, a group IV material, or combinations thereof;
• and
• a first gate portion;
• wherein:
• (a)(i) a first axis intersects the first, second, and third layers but not the first gate portion, (a)(ii) a second axis, parallel to the first axis, intersects the first gate portion and a channel, which is included in the second layer and which includes the second material, but does not intersect the first and third layers.

A method comprising:

• forming a dielectric layer on a substrate;
• forming a trench within the dielectric layer;
• forming a first layer within the trench, the first layer including a doped first material that includes at least one of a group III-V material, a group IV material, or combinations thereof;
• forming a second layer within the trench and on the first layer, the second layer including a second material that includes at least one of a group III-V material, a group IV material, or combinations thereof;
• forming a first gate portion on the second layer;
• forming a third layer on the second layer, the third layer including a doped third material that includes at least one of a group III-V material, a group IV material, or combinations thereof;
• and
• removing a portion of the first layer to form a void;
• wherein:
• (a)(i) a first axis intersects the first, second, and third layers but not the first gate portion, (a)(ii) a second axis, parallel to the first axis, intersects the first gate portion and a channel, which includes the second material, but does not intersect the first and third layers.