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US 10,651,311 B2Granted
Metal gate with silicon sidewall spacers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen-Han Fang, Po-Chi Wu
Life of this patent
Estimating the term…
Abstract
A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.
Claims20
A device comprising:
- an isolation region;
- a first protruding semiconductor fin and a second protruding semiconductor fin higher than a top surface of the isolation region, wherein the first and the second protruding semiconductor fins are immediately neighboring each other, with no other protruding semiconductor fin therebetween;
- and
- a gate stack extending onto a top surface and sidewalls of the first protruding semiconductor fin and the second protruding semiconductor fin, wherein the gate stack comprises:
- a gate dielectric;
- a conductive diffusion barrier layer over the gate dielectric, wherein the conductive diffusion barrier layer comprises a metal nitride;
- a first silicon corner spacer and a second silicon corner spacer over the conductive diffusion barrier layer, wherein both of the first and the second silicon corner spacers are between the first and the second protruding semiconductor fins, and are at bottom corners of the conductive diffusion barrier layer;
- and
- a conductive layer over the first and the second silicon corner spacers, wherein the conductive diffusion barrier layer and the conductive layer enclose the first silicon corner spacer and the second silicon corner spacer therein, and physically separate the first silicon corner spacer from the second silicon corner spacer in a cross-sectional view of the device, and wherein the conductive diffusion barrier layer, the first and the second silicon corner spacers, and the conductive layer form a portion of a gate electrode of a Fin Field-Effect Transistor (FinFET).
6 more elements
A device comprising:
- a transistor comprising:
- a gate dielectric;
- a first conductive layer over the gate dielectric;
- a first silicon layer and a second silicon layer over the first conductive layer;
- and
- a second conductive layer over the first silicon layer and the second silicon layer, wherein the second conductive layer comprises a lower surface comprising:
- a first portion and a second portion in contact with the first silicon layer and the second silicon layer, respectively;
- and
- a third portion in direct contact with the first conductive layer in a region between the first silicon layer and the second silicon layer, wherein in a cross-sectional view of the device, the first silicon layer and the second silicon layer are physically separated from each other by the first conductive layer and the third portion of the second conductive layer.
6 more elements
A device comprising:
- an isolation region;
- a first protruding semiconductor fin higher than a top surface of the isolation region;
- a second protruding semiconductor fin higher than the top surface of the isolation region, wherein the isolation region is between the first protruding semiconductor fin and the second protruding semiconductor fin;
- a gate stack extending onto a top surface and sidewalls of the first protruding semiconductor fin, wherein the gate stack comprises:
- a gate dielectric;
- a first conductive layer over the gate dielectric;
- a first silicon corner spacer over a bottom portion of the first conductive layer;
- a second silicon corner spacer over the bottom portion of the first conductive layer, wherein both the first silicon corner spacer and the second silicon corner spacer overlap the isolation region, and the first silicon corner spacer is physically separated from the second silicon corner spacer;
- and
- a second conductive layer over the first silicon corner spacer, wherein the first conductive layer and the second conductive layer enclose the first silicon corner spacer and the second silicon corner spacer therein;
- and
- source and drain regions on opposite sides of the gate stack.
9 more elements
Dependencies are inferred from the claim text.