Methods of simultaneously forming bottom and top spacers on a vertical transistor device

A vertical transistor device, comprising:

• a vertically oriented channel semiconductor structure;
• a bottom source/drain (S/D) region positioned on and in contact with a lower end portion of said vertically oriented channel semiconductor structure;
• a top source/drain (S/D) region positioned on and in contact with an upper end portion of said vertically oriented channel semiconductor structure;
• a gate structure positioned above said bottom source/drain (S/D) region, below said top source/drain (S/D) region, and surrounding a center portion of said vertically oriented channel semiconductor structure;
• and
• a unitary and contiguous insulating structure surrounding at least said gate structure and said vertically oriented channel semiconductor structure, said insulating structure comprising:
• a top spacer portion positioned between said gate structure and at least a portion of said top source/drain (S/D) region;
• and
• a bottom spacer portion positioned between said gate structure and at least a portion of said bottom source/drain (S/D) region.

A vertical transistor device, comprising:

• a vertically oriented channel semiconductor structure;
• a bottom source/drain (S/D) region positioned on and in contact with a lower end portion of said vertically oriented channel semiconductor structure;
• a top source/drain (S/D) region positioned on and in contact with an upper end portion of said vertically oriented channel semiconductor structure;
• a gate structure positioned above said bottom source/drain (S/D) region, below said top source/drain (S/D) region, and surrounding a center portion of said vertically oriented channel semiconductor structure that is positioned between said upper and lower end portions of said vertically oriented channel semiconductor structure, said gate structure comprising a gate electrode and a gate insulation layer that is positioned between said gate electrode and said center portion of said vertically oriented channel semiconductor structure;
• and
• a unitary and contiguous insulating structure, said insulating structure comprising:
• a top spacer portion positioned between said gate structure and at least a portion of said top source/drain (S/D) region;
• a bottom spacer portion positioned between said gate structure and at least a portion of said bottom source/drain (S/D) region;
• and
• a gate cap portion positioned around an outer perimeter surface of said gate structure and extending from said top spacer portion to said bottom spacer portion, wherein each of said top spacer portion, said bottom spacer portion, and said gate cap portion of said insulating structure comprise a same insulating material.