Inner spacer formation in a nanosheet field-effect transistor

A method of forming a field-effect transistor, the method comprising:

• forming a first body feature that includes a first nanosheet channel layer, a second nanosheet channel layer, and a sacrificial layer arranged vertically between the first nanosheet channel layer and the second nanosheet channel layer;
• laterally recessing the sacrificial layer relative to the first nanosheet channel layer and the second nanosheet channel layer at a sidewall of the first body feature to expose a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer;
• forming a sacrificial spacer by oxidizing a portion of the sacrificial layer at the sidewall of the first body feature;
• epitaxially growing a first section and a second section of a semiconductor material respectively on the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer to narrow a gap vertically separating the portion of the first nanosheet channel layer from the portion of the second nanosheet channel layer;
• removing the sacrificial spacer to form a cavity between the first section and the second section of the semiconductor material and the sacrificial layer;
• conformally depositing a dielectric spacer in the cavity;
• epitaxially growing a source/drain region using the first section and the second section of the semiconductor material as respective growth seeds;
• and
• after epitaxially growing the source/drain region, removing the sacrificial layer selective to the first section and the second section of the semiconductor material,
• wherein the dielectric spacer protects the source/drain region when removing the sacrificial layer.

A method of forming a field-effect transistor, the method comprising:

• forming a first body feature that includes a first nanosheet channel layer, a second nanosheet channel layer, and a sacrificial layer arranged vertically between the first nanosheet channel layer and the second nanosheet channel layer;
• laterally recessing the sacrificial layer relative to the first nanosheet channel layer and the second nanosheet channel layer at a sidewall of the first body feature to expose a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer;
• forming a sacrificial spacer by oxidizing a portion of the sacrificial layer at the sidewall of the first body feature;
• epitaxially growing a first section and a second section of a semiconductor material respectively on the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer to narrow a gap vertically separating the portion of the first nanosheet channel layer from the portion of the second nanosheet channel layer;
• removing the sacrificial spacer to form a cavity between the first section and the second section of the semiconductor material and the sacrificial layer;
• and
• conformally depositing a dielectric spacer in the cavity,
• wherein a gate structure is stacked with the first body feature and includes a first sidewall spacer, and further comprising:
• after removing the sacrificial spacer, forming a second sidewall spacer on the first sidewall spacer.