Pseudomorphic InGaAs on GaAs for gate-all-around transistors

A semiconductor device comprising:

• a shallow trench isolation (STI) layer;
• a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a gate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel, and wherein the bottommost nanowire channel has a chevron shape;
• and
• a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel.

A semiconductor device comprising:

• a shallow trench isolation (STI) layer;
• a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a gate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel;
• and
• a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the STI layer.