Semiconductor interconnect structure having graphene-capped metal interconnects
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Yi Yang, Ching-Fu Yeh, Ming-Han Lee, Shau-Lin Shue
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.
Claims20
A semiconductor structure, comprising:
- a substrate;
- a metal layer formed on the substrate;
- a dielectric layer formed on the metal layer;
- a first conductive layer formed in the dielectric layer and on a portion of the metal layer;
- a graphene barrier layer formed at least on side surfaces of the dielectric layer and on the first conductive layer;
- and
- a second conductive layer formed in the dielectric layer and on the graphene barrier layer.
A semiconductor structure, comprising:
- a conductive interconnect layer;
- a dielectric layer formed over the conductive interconnect layer;
- a first conductive layer formed in the dielectric layer and in contact with a portion of the conductive interconnect layer;
- a second conductive layer formed in the dielectric layer and over the first conductive layer, the second conductive layer comprising at least one sidewall;
- and
- a graphene barrier layer formed between the first and second conductive layers and between the at least one sidewall of the second conductive layer and the dielectric layer.
A semiconductor interconnect structure, comprising:
- a substrate;
- a conductive interconnect layer on the substrate;
- a patterned dielectric layer over the substrate and over a portion of the conductive interconnect layer, the patterned dielectric layer comprising a pair of opposing sidewall surfaces;
- a first conductive layer on the conductive interconnect layer;
- a graphene layer formed on the first conductive layer and on the pair of opposing sidewall surfaces of the patterned dielectric layer;
- and
- a second conductive layer formed on the graphene layer, wherein at least a portion of the second conductive layer is between the pair of opposing sidewall surfaces of the patterned dielectric layer.
Dependencies are inferred from the claim text.