Leakage-free implantation-free ETSOI transistors
AssigneeInternational Business Machines Corporation
InventorsJoel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
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Abstract
A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.
Claims18
A method for forming a transistor, comprising:
- patterning a thin semiconductor layer of an extremely thin semiconductor-on-insulator (ETSOI) substrate having a base substrate, the thin semiconductor layer and a buried dielectric therebetween, the patterning forming a plurality of thin semiconductor layer portions including a device channel and defining openings between the plurality of thin semiconductor layer portions at opposing positions relative to the device channel;
- depositing an n-type material including Al-doped ZnO on the buried dielectric within the openings, and planarizing the n-type material to form source and drain regions at a substantially same thickness as the plurality of thin semiconductor layer portions and having a substantially uniform width from the buried dielectric to exposed surfaces of the plurality of thin semiconductor layer portions;
- and
- forming a gate structure over the device channel after the source and drain regions are formed.
A method for forming a transistor, comprising:
- patterning a thin semiconductor layer of an extremely thin semiconductor-on-insulator (ETSOI) substrate having a base substrate, the thin semiconductor layer and a buried dielectric therebetween, the patterning forming first, second and third thin semiconductor layer portions and defining openings between the first, second and third thin semiconductor layer portions at opposing positions relative to a device channel corresponding to the first thin semiconductor layer portion;
- depositing an n-type material on the buried dielectric within the openings, and planarizing the n-type material to form source and drain regions at a substantially same thickness as the plurality of thin semiconductor layer portions, the source and drain regions each being adjacent to a respective sidewall of the device channel and a sidewall of a respective one of the second and third thin semiconductor layer portions and having a substantially uniform width from the buried dielectric to exposed surfaces of the plurality of thin semiconductor layer portions;
- and
- forming a gate structure over the device channel after the source and drain regions are formed.
Dependencies are inferred from the claim text.