Resistive random access memory device

#In recent years, unconventional nonvolatile memory (NVM) devices, such as ferroelectric random access memory (FRAM) devices, phase-change random access memory (PRAM) devices, and resistive random access memory (RRAM) devices, have emerged. In particular, RRAM devices, which exhibit a switching behavior between a high resistance state (HRS) and a low resistance state (LRS), have various advantages over conventional NVM devices. Such advantages include, for example, compatible fabrication steps with current complementary-metal-oxide-semiconductor (CMOS) technologies, low-cost fabrication, a compact structure, flexible scalability, fast switching, high integration density, etc.

#In general, an RRAM device includes a lower electrode (e.g., an anode) and an upper electrode (e.g., a cathode) with a variable resistive material layer interposed therebetween. The existing RRAM device is typically formed by sequentially depositing plural layers to form the lower electrode, the variable resistive material layer, and the upper electrode, and then etching the plural layers all together, such that the respective lower and upper boundaries of the lower electrode, variable resistive material layer, and the upper electrode of the existing RRAM device are horizontally aligned with one another. Such a method to form an RRAM array that includes a plurality of arranged RRAM devices is typically subjected to the limit of a lithography technique used to define the pitch of each RRAM device of the RRAM array. Further, there exists multiple conductive pathways resulting in a difficult evaluation of device performances.

#Thus, existing RRAM devices and methods to make the same are not entirely satisfactory.

#Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various features are not necessarily drawn to scale. In fact, the dimensions and geometries of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIGS. 1A, 1B, and 1C illustrate a flow chart of an exemplary method for forming a semiconductor device, in accordance with some embodiments.

#FIG. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, and 2N illustrate cross-sectional views of an exemplary semiconductor device during various fabrication stages, made by the method of FIG. 1, in accordance with some embodiments.

#The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

#Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

#The present disclosure provides various embodiments of a novel resistive random access memory (RRAM) device and methods to form the same. In some embodiments, the disclosed RRAM device includes one or more RRAM cells that each extends along the sidewall of a respective dielectric fin. Each of the one or more RRAM cells is formed of an RRAM resistor and an RRAM selector that are sandwiched between a lower electrode and an upper electrode, wherein the RRAM resistor is formed by either the lower or upper electrode, an intermediate electrode, and a variable resistive material layer, and the RRAM selector is formed by either the upper or lower electrode, the intermediate electrode, and a selector layer. In some embodiments, an upper boundary of the lower electrode, respective lower and upper boundaries of the selector layer, intermediate electrode, variable resistive material layer, and a lower boundary of the upper electrode are each tilted away from the sidewall of the extended dielectric fin by an acute angle. As such, when viewed cross-sectionally, at least the selector layer and variable resistive material layer can each present a rhomboid-based or rhombus-based profile, which may provide a directional conduction path (i.e., shortest distance) crossing each of the selector layer and variable resistive material layer and enable an accurate evaluation of device performances.