Semiconductor package including a redistribution line
AssigneeSamsung Electronics Co., Ltd.
InventorsJi Hwang Kim, Chajea Jo, Hyoeun Kim, Jongbo Shim, Sang-uk Han
Life of this patent
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Abstract
A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.
Claims19
A semiconductor package, comprising:
- a first semiconductor chip;
- a second semiconductor chip below the first semiconductor chip;
- and
- a third semiconductor chip below the second semiconductor chip,
- wherein the second semiconductor chip comprises:
- a first surface in direct contact with the first semiconductor chip;
- a second surface facing the third semiconductor chip;
- and
- a first redistribution pattern on the second surface of the second semiconductor chip and electrically connected to the third semiconductor chip,
- wherein the third semiconductor chip comprises:
- a third surface facing the second semiconductor chip;
- and
- a conductive pad on the third surface,
- wherein the first semiconductor chip comprises a first semiconductor substrate and a first insulation layer on the first semiconductor substrate,
- wherein the second semiconductor chip comprises a second semiconductor substrate and a second insulation layer on the second semiconductor substrate,
- wherein a top surface of the second insulation layer corresponds to the first surface to the second semiconductor chip,
- wherein a bottom surface of the second semiconductor substrate corresponds to the second surface of the second semiconductor chip, and
- wherein the second insulation layer is in direct contact with the first insulation layer.
A semiconductor package, comprising;
- a first semiconductor chip;
- a second semiconductor chip below the first semiconductor chip;
- and
- a third semiconductor chip below the second semiconductor chip,
- wherein the first semiconductor chip and the second semiconductor chip have sidewalls aligned with each other,
- wherein the third semiconductor chip has a width less than that of the second semiconductor chip, and
- wherein the third semiconductor chip comprises a first surface facing the second semiconductor chip, a conductive pad in direct contact with the first surface and a first redistribution pattern in direct contact with the conductive pad on the first surface.
A semiconductor package, comprising:
- an image sensor chip;
- a logic chip disposed on the image sensor chip;
- a memory chip spaced apart from the logic chip, wherein sidewalk of the image sensor chip and the logic chip are substantially aligned with each other along a direction orthogonal to an upper surface of the image sensor chip, and wherein a sidewall of the memory chip is spaced apart from the sidewails of the image sensor chip and the logic chip;
- a first redistribution pattern disposed on a surface of the logic chip facing the memory chip;
- and
- a second redistribution pattern disposed on a surface of the memory chip facing the logic chip, wherein the first redistribution pattern is electrically connected with the second redistribution pattern.
Dependencies are inferred from the claim text.