3D circuit transistors with flipped gate

An integrated circuit provided with several superimposed levels of transistors, the integrated circuit comprising:

• a lower level including at least a transistor having a channel region formed in a first semiconducting layer resting on a substrate;
• and
• an upper level, disposed above the lower level and provided with transistors having respective channel regions formed in zones that are unconnected and insulated from each other, the zones comprising a second semiconducting layer disposed above the first semiconducting layer and covered with a dielectric material, each zone comprising a gate electrode disposed on a rear face of the second semiconducting layer and disposed between the first semiconducting layer and the second semiconducting layer, the rear face being parallel to a plane of an interface between the lower level and the upper level,
• wherein a first transistor among the transistors of the upper level is provided with a source or drain contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being biased by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer, the front face being parallel to the rear face and disposed opposite to the rear face.