Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device, comprising:

• an electrode structure comprising a plurality of gate electrodes and a plurality of insulating layers,
• wherein the gate electrodes and the insulating layers are alternately stacked on a substrate, and a side surface of the electrode structure is recessed in areas corresponding to the gate electrodes to define a plurality of recess regions;
• a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and crossing the side surface of the electrode structure;
• a plurality of first charge trap layers respectively disposed in the recess regions of the electrode structure, wherein the first charge trap layers surround the semiconductor pattern;
• a tunnel insulating layer disposed between the first charge trap layers and the semiconductor pattern;
• a blocking insulating layer disposed between the first charge trap layers and the electrode structure;
• and
• a second charge trap layer,
• wherein the second charge trap layer continuously extends between the blocking insulating layer and the first charge trap layers, and the second charge trap layer continuously extends between the tunnel insulating layer and the first charge trap layers,
• wherein the first charge trap layers are formed of a material having a first energy band gap, and the second charge trap layer is formed of a material having a second energy band gap larger than the first energy band gap.