Word line structure of three-dimensional memory device

A memory device comprising:

• a substrate;
• a plurality of semiconductor channels, wherein one end portion of each of the plurality of semiconductor channels extends a direction substantially perpendicular to a top surface of the substrate;
• a drain region over the end portion of each of the plurality of semiconductor channels;
• a plurality of charge storage regions, each charge storage region being surrounded by a respective one of the plurality of semiconductor channels;
• a source region in the substrate;
• a plurality of bit lines each over a respective end portion of each of the plurality of semiconductor channels;
• a plurality of word lines extending along a direction substantially parallel to the top surface of the substrate and comprising an upper selective gate, a lower selective gate, and a plurality of word lines between the upper selective gate and the lower selective gate;
• a plurality of metal contact vias connecting to the plurality of word lines;
• a driver circuit above the plurality of bit lines, wherein:
• two or more of the plurality of word lines of substantially a same height over the substrate are conductively connected through at least one connection portion of substantially the same height, wherein each connection portion being sandwiched by two portions of a gate line slit extending along the first direction;
• and
• the two or more of the plurality of word lines share a metal contact via that electrically connects to a respective metal interconnect, the metal contact via being formed on one of the two or more of the plurality of word lines.