Back to results
US 10,651,182 B2Granted
Three-dimensional ferroelectric NOR-type memory
AssigneeIntel Corporation
InventorsDaniel H. Morris, Uygar E. Avci, Ian A. Young
Life of this patent
Estimating the term…
Abstract
An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.
Claims22
A system comprising:
- a substrate;
- first, second, and third word lines;
- first, second, and third layers, wherein the first layer is between the substrate and the first word line, the second layer is between the first and second word lines, and the third layer is between the second and third word lines;
- first, second, and third portions of a material, wherein the first portion of the material is between the first word line and the first layer, the second portion of the material is between the second word line and the second layer, and the third portion of the material is between the third word line and the third layer;
- a monolithic semiconductor layer on the first, second, and third portions of the material;
- a bit line having a long axis and a short axis;
- wherein the first layer includes a metal, the second layer includes the metal, and the third layer includes the metal;
- wherein the material includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof;
- wherein (a) a first plane, parallel to the short axis, intersects the first layer, the semiconductor layer, and the bit line;
- (b) a second plane, parallel to the short axis, intersects the second layer, the semiconductor layer, and the bit line;
- and (c) a third plane, parallel to the short axis, intersects the third layer, the semiconductor layer, and the bit line.
8 more elements
A system comprising:
- first, second, and third word lines;
- first, second, and third layers including a conductor material, wherein:
- (a) the first word line is between the first and second layers, (b) the second layer is between the first and second word lines;
- and (c) the third layer is between the second and third word lines;
- first, second, and third portions of ferroelectric material, wherein the first portion of ferroelectric material is between the first word line and the first layer, the second portion of ferroelectric material is between the second word line and the second layer, and the third portion of ferroelectric material is between the third word line and the third layer;
- a continuous semiconductor layer on the first, second, and third portions of ferroelectric material, wherein the semiconductor layer includes a portion of the semiconductor layer that extends, uninterrupted, from the first layer to the third word line;
- a bit line having a long axis and a short axis;
- wherein (a) a first plane, parallel to the short axis, intersects the first layer, the bit line, and the semiconductor layer;
- (b) a second plane, parallel to the long axis, intersects the first, second, and third word lines and the first, second, and third portions of ferroelectric material but does not intersect any of the first, second, or third layers;
- and (c) a third plane, parallel to the long axis, intersects the first, second, and third layers.
7 more elements
Dependencies are inferred from the claim text.