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US 10,651,171 B2Granted
Integrated circuit with a gate structure and method making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Ying-Keung Leung, Chi On Chui
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Abstract
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.
Claims20
A semiconductor structure comprising:
- a first fin and a second fin disposed over a substrate;
- a first gate stack wrapping a portion of the first fin and a second gate stack wrapping a portion of the second fin, wherein the first gate stack includes a first gate dielectric and a first gate electrode and the second gate stack includes a second gate dielectric and a second gate electrode;
- first gate spacers disposed along sidewalls of the first gate stack, wherein the first gate spacers include a first gate spacer portion and a second gate spacer portion, wherein a material of the first gate spacer portion is different than a material of the second gate spacer portion;
- second gate spacers disposed along sidewalls of the second gate stack, wherein the second gate spacers include a third gate spacer portion and a fourth gate spacer portion, wherein a material of the third gate spacer portion is different than a material of the fourth gate spacer portion;
- a first dielectric layer disposed between the second gate spacer portion and the sidewalls of the first gate stack, wherein the first dielectric layer physically contacts the first gate dielectric of the first gate stack and the second gate spacer portion, and further wherein the first dielectric layer has a first thickness;
- and
- a second dielectric layer disposed between the fourth gate spacer portion and the sidewalls of the second gate stack, wherein the second dielectric layer physically contacts the second gate dielectric of the second gate stack and the fourth gate spacer portion, and further wherein the second dielectric layer has a second thickness that is greater than the first thickness.
4 more elements
A semiconductor structure comprising:
- a first field-effect transistor (FET) that includes a first fin structure, a first gate stack disposed over a first channel region of the first fin structure, such that the first gate stack is disposed between first source/drain features disposed over first source/drain regions of the first fin structure, a first gate spacer disposed along an entire sidewall of the first gate stack, and a first dielectric material layer disposed along a portion of the sidewall of the first gate stack, wherein the first dielectric material layer physically contacts the first gate spacer and the portion of the sidewall of the first gate stack;
- and
- a second FET that includes a second fin structure, a second gate stack disposed over a second channel region of the second fin structure, such that the second gate stack is disposed between second source/drain features disposed over second source/drain regions of the second fin structure, a second gate spacer disposed along an entire sidewall of the second gate stack, and a second dielectric material layer disposed along a portion of the sidewall of the second gate stack, wherein the second dielectric material layer physically contacts the second gate spacer and the portion of the sidewall of the second gate stack, and further wherein:
- the first dielectric material layer of the first gate stack has a first thickness T1, and
- the second dielectric material layer has a second thickness T2, wherein the second thickness T2 is greater than the first thickness T1.
2 more elements
A semiconductor structure comprising:
- a fin structure on a substrate;
- a first gate stack and a second gate stack formed on the fin structure;
- and
- a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric material layer includes a first portion disposed on a sidewall of the first gate stack with a first uniform thickness and a second portion disposed on a sidewall of the second gate stack with a second uniform thickness greater than the first uniform thickness, and further wherein:
- the first gate stack includes a first gate dielectric layer, wherein a portion of the first gate dielectric layer extends under the first portion of the dielectric material layer, such that the portion of the first gate dielectric layer is disposed between the fin structure and the first portion of the dielectric material layer, and
- the second gate stack includes a second gate dielectric layer having a thickness greater than that of the first gate dielectric layer, wherein a portion of the second gate dielectric layer extends under the second portion of the dielectric material layer, such that the portion of the second gate dielectric layer is disposed between the fin structure and the second portion of the dielectric material layer.
3 more elements
Dependencies are inferred from the claim text.