Memory package and memory device utilizing an intermediate chip
AssigneeSamsung Electronics Co., Ltd.
InventorsHye Seung Yu, Won Joo Yun, Hyun Ui Lee
Life of this patent
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Abstract
A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.
Claims20
A memory package comprising:
- a plurality of memory chips stacked on a package substrate;
- a logic chip disposed between the plurality of memory chips and the package substrate, the logic chip configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips;
- and
- an intermediate chip connected to the plurality of vias, the intermediate chip being disposed between the plurality of memory chips and the logic chip, and being configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.
A memory package comprising:
- a plurality of memory chips stacked in a first direction, each of the plurality of memory chips including a plurality of vias extending in the first direction;
- and
- an intermediate chip disposed below the plurality of memory chips, and including a driving circuit exchanging data with at least a subset of the plurality of memory chips via the plurality of vias, and a control circuit selectively driving at least a subset of a plurality of transmitters and at least a subset of a plurality of receivers included in the driving circuit, based on a predetermined data transmission rate.
A memory package comprising:
- a package substrate;
- a plurality of memory chips stacked on a first region of the package substrate;
- a processor chip disposed in a second region of the package substrate;
- a logic chip disposed between the plurality of memory chips and the package substrate, the logic chip being configured to process a signal received from the processor chip to control the plurality of memory chips to store and/or output data;
- and
- an intermediate chip formed in a semiconductor die separate from that of the logic chip, the intermediate chip being disposed between the logic chip and the plurality of memory chips, and including a receiving circuit serializing data received from the plurality of memory chips and transmitting the serialized data to the logic chip, and a transmitting circuit deserializing data to be stored in the plurality of memory chips and transmitting the deserialized data to the plurality of memory chips.
Dependencies are inferred from the claim text.