Thermal pads between stacked semiconductor dies and associated systems and methods
AssigneeMicron Technology, Inc.
InventorsJaspreet S. Gandhi, Michel Koopmans
Life of this patent
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Abstract
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
Claims23
A semiconductor die, comprising:
- a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;
- an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;
- a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate, and wherein the metallization structure is laterally spaced apart from the sidewall by a dielectric layer that surrounds the sidewall of the end portion of the interconnect;
- and
- a thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad projects to a first vertical height above the first surface and the metallization structure projects to a second vertical height above the first surface, the first and second heights being generally the same.
A semiconductor die, comprising:
- a semiconductor substrate having a surface and an indentation in the surface;
- an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the indentation, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the indentation;
- a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the sidewall by a dielectric layer that surrounds the sidewall of the end portion of the interconnect;
- a passivation material at least partially on the surface of the semiconductor substrate, wherein a first portion of the passivation material is in the indentation between the metallization structure and the semiconductor substrate, and wherein a second portion of the passivation material is in the indentation and laterally spaced apart from the metallization structure;
- and
- a thermal pad on the surface of the semiconductor substrate, wherein the thermal pad extends away from the surface to a first height and the metallization structure extends away from the surface to a second height, the first and second heights being generally the same.
A semiconductor die, comprising:
- a semiconductor substrate having a generally horizontal surface and a generally vertical surface, wherein the vertical surface at least partially defines an indentation in the horizontal surface;
- an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the indentation, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the indentation;
- a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the vertical surface of the semiconductor substrate, and wherein the metallization structure is laterally spaced apart from the sidewall by a dielectric layer that surrounds the sidewall of the end portion of the interconnect;
- and
- a thermal pad on the horizontal surface of the semiconductor substrate, wherein the thermal pad extends away from the horizontal surface to a first height and the metallization structure extends away from the horizontal surface to a second height, the first and second heights being generally the same.
Dependencies are inferred from the claim text.