Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding

A system comprising:

• a processor;
• and
• a non-volatile storage device coupled with the processor, the storage device comprising:
• a first die comprising a first three-dimensional (3D) array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry to access the first 3D array of non-volatile storage cells;
• and
• a second die vertically stacked and bonded with the first die, the second die comprising a second 3D array of non-volatile storage cells, the CMOS circuitry of the first die to access the second 3D array of non-volatile storage cells of the second die;
• the CMOS circuitry of the first die is disposed between the first 3D array of non-volatile storage cells and the second 3D array of non-volatile storage cells.

A three-dimensional (3D) NAND memory device comprising:

• a first die comprising a first three-dimensional (3D) array of non-volatile NAND memory cells and control circuitry;
• and
• a second die vertically stacked and bonded with the first die, the second die comprising a second 3D array of non-volatile NAND memory cells, at least a portion of the control circuitry of the first die to access both the first 3D array of non-volatile NAND memory cells of the first die and the second 3D array of non-volatile NAND memory cells of the second die;
• the control circuitry of the first die is disposed between the first 3D array of non-volatile NAND memory cells and the second 3D array of non-volatile NAND memory cells.