Tamper detection for a chip package

A structure comprising:

• a lead frame with a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle;
• a chip attached to the die attach paddle, the chip including a surface having an outer boundary, a first plurality of bond pads arranged in a first plurality of rows proximate to the outer boundary, and a second plurality of bond pads that are interior of the outer boundary relative to the first plurality of bond pads, the first plurality of bond pads located on the surface of the chip between the second plurality of bond pads and the outer boundary of the chip, the second plurality of bond pads arranged in a second plurality of rows, and each of the second plurality of rows angled relative to one of the first plurality of rows toward a center of the surface of the chip;
• a first plurality of wires each having a first end coupled to one of the outer lead fingers and a second end coupled to one of the second plurality of bond pads;
• a tamper detection circuit coupled with the first plurality of wires;
• and
• a second plurality of wires extending from the inner lead fingers to the first plurality of bond pads on the chip, the second plurality of wires located between the lead frame and the first plurality of wires.