Methods of forming alignment marks during patterning of semiconductor material
AssigneeMicron Technology, Inc.
InventorHideo Hironaka
Life of this patent
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AssigneeMicron Technology, Inc.
InventorHideo Hironaka
Estimating the term…
Some embodiments include provision of a mass of semiconductor material having a first region and a second region. A first pattern set is formed to extend across the first region, and a third pattern set is formed to extend across the second region. The first pattern set includes first lines and first trenches between the first lines. The third pattern set includes alignment marks. The first trenches are utilized to form rails from the semiconductor material within the first region. The alignment marks are parallel to the rails. A second pattern set is formed to extend across the first region, and a fourth pattern set is formed to extend across the second region. The second pattern set includes first openings, and the fourth pattern set includes second openings. The first openings are utilized to subdivide the rails into pillars. The second openings transform the alignment marks into an overlay pattern.
A method comprising:
A patterning method, comprising:
A patterning method, comprising:
Dependencies are inferred from the claim text.