Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS)

A method of forming an interconnect structure for an integrated circuit (IC), comprising:

• forming a metal layer comprising a plurality of metal lines disposed at a metal line pitch and a plurality of dielectric structures, wherein a width of the plurality of metal lines in a first direction is greater than a distance between adjacent metal lines of the plurality of metal lines in the first direction, the plurality of metal lines comprising top surfaces and the plurality of dielectric structures comprising top surfaces;
• disposing a protective coating on the top surfaces of the plurality of metal lines;
• disposing a block copolymer layer on the top surfaces of the plurality of dielectric structures;
• forming first type and second type phase separation structures in the block copolymer layer;
• etching the first type phase separation structures between the second type phase separation structures to expose portions of the top surfaces of the plurality of dielectric structures;
• and
• etching dielectric material of the plurality of dielectric structures below the exposed portions of the top surfaces of the plurality of dielectric structures, employing the second type phase separation structures as a mask to form slices of the dielectric material separated by gaps.