Low-inductance current paths for on-package power distributions and methods of assembling same

A computing system, comprising:

• semiconductor package substrate including a die side and a land side;
• a VCC via in the semiconductor package substrate, wherein the VCC via is between a VCC top trace and a VCC bottom trace;
• a VSS via in the semiconductor package substrate, wherein the VSS via is between a VSS top trace and a VSS bottom trace, wherein the VSS via is adjacent the VCC via;
• a micro trace that contacts only one of the VCC via and VSS via, wherein the micro trace is between the VCC and VSS top traces and the VCC and VSS bottom traces, and wherein the micro trace is thinner than any of the VSS and VCC top traces and the VSS and VCC bottom traces;
• a micro dielectric layer contacting the micro trace, wherein the micro dielectric layer contacts one of the VCC and VSS top traces, and the VCC and VSS bottom traces;
• a capacitor on the die side, wherein the capacitor is coupled to the micro trace;
• a semiconductive device on the die side, wherein the semiconductive device is coupled to the micro trace;
• and
• wherein the semiconductive device is part of a chipset.