Apparatus and method of three dimensional conductive lines
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang, Yen-Huei Chen
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Abstract
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
Claims20
An inter-tier memory column, comprising:
- a first bit line, comprising:
- a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC)
- a second segment disposed within a second tier of said 3D IC disposed along a second axis horizontally offset from a first axis,
- wherein said first segment is electrically connected to said second segment by a first conductive member extending continuously from said first segment to said second segment;
- and
- a second bit line comprising:
- a third segment disposed within said first tier of said 3D IC along a third axis parallel to said second axis;
- and
- a fourth segment disposed within said second tier of said 3D IC along a fourth axis parallel to said first axis, wherein said third segment is electrically connected to said fourth segment by a second conductive member extending continuously from said third segment to said fourth segment.
An inter-tier memory column, comprising:
- a first bit line, comprising:
- a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC)
- a second segment disposed within a second tier of said 3D IC disposed along a second axis horizontally offset from a first axis;
- a first plurality of memory cells electrically connected to said first bit line;
- a second bit line comprising:
- a third segment disposed within said first tier of said 3D IC along a third axis parallel to said second axis;
- and
- a fourth segment disposed within said second tier of said 3D IC along a fourth axis parallel to said first axis;
- and
- a second plurality of memory cells electrically connected to said second bit line;
- wherein said first segment is electrically connected to said second segment by a first conductive member extending continuously from said first segment to said second segment, and wherein said third segment is electrically connected to said fourth segment by a second conductive member extending continuously from said third segment to said fourth segment.
A method of forming an inter-tier memory column, comprising:
- forming a first bit line comprising a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC) and a second segment disposed within a second tier of said 3D IC disposed along a second axis horizontally offset from a first axis;
- forming a second bit line comprising a third segment disposed within said first tier of said 3D IC along a third axis parallel to said second axis and a fourth segment disposed within said second tier of said 3D IC along a fourth axis parallel to said first axis;
- and
- connecting said first segment to said second segment with a first vertical conductive element.
Dependencies are inferred from the claim text.