Efficient heat-sinking in PIN diode
AssigneeJuniper Networks, Inc.
InventorsErik Johan Norberg, Naser Dalvand, Gregory Alan Fish
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Abstract
The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.
Claims20
A device comprising:
- a semiconductor-on-insulator substrate comprising a semiconductor handle, a buried oxide layer disposed on top of the semiconductor handle, and a semiconductor device layer disposed on top of the buried oxide layer;
- a top oxide cladding disposed on the semiconductor device layer;
- a p-i-n diode embedded in the top cladding layer, the p-i-n diode comprising a doped top layer, an intrinsic layer, and a doped bottom layer;
- a metal structure embedded in the top oxide cladding and electrically connected to the doped top layer;
- and
- one or more thermal vias extending from the metal structure through the top oxide cladding at least to the semiconductor device layer, but not extending through the buried oxide layer to the semiconductor handle.
A device comprising:
- a semiconductor-on-insulator substrate comprising a semiconductor handle, a buried oxide layer disposed on top of the semiconductor handle, and a semiconductor device layer disposed on top of the buried oxide layer;
- a top oxide cladding disposed on the semiconductor device layer;
- a p-i-n diode embedded in the top cladding layer, the p-i-n diode comprising a doped top layer, an intrinsic layer, and a doped bottom layer;
- a metal structure embedded in the top oxide cladding and electrically connected to the doped top layer;
- and
- one or more thermal vias extending from a top surface of the intrinsic layer to the metal structure.
A method comprising:
- forming a p-i-n diode embedded within a top oxide cladding on a semiconductor-on-insulator substrate, the p-i-n diode comprising doped top and bottom layers and an intrinsic layer therebetween;
- etching one or more first electrical via holes extending down to a top surface of the doped bottom layer;
- etching one or more thermal via holes, the one or more thermal via holes comprising at least one of one or more first thermal via holes extending down to at least a semiconductor device layer of the semiconductor-on-insulator substrate or one or more second thermal via holes extending down to a top surface of the intrinsic layer;
- etching a second electrical via hole extending down to a top surface of the doped top layer;
- and
- filling the first and second electrical via holes with one or more electrically conductive materials to form respective first and second electrical vias and filling the one or more thermal via holes with one or more thermally conductive materials to form one or more thermal vias.
Dependencies are inferred from the claim text.