Semiconductor chip that includes a cover protection layer covering a portion of a passivation layer

A semiconductor chip comprising:

• a semiconductor substrate comprising a die region in which a plurality of chip pads are arranged and a residual scribe lane surrounding a periphery of an edge of the die region in which a plurality of residual test pads are arranged;
• a passivation layer at least partially covering the semiconductor substrate and exposing the plurality of chip pads and the plurality of residual test pads;
• and
• a cover protection layer at least partially covering and integrating with a portion of the passivation layer,
• wherein the cover protection layer comprises a first portion at least partially covering an interior area of the die edge, a second portion in contact with a portion of an edge adjacent to a corner of the semiconductor substrate in the residual scribe lane, and a third portion extending from the second portion along the residual scribe lane and spaced apart from the plurality of residual test pads, wherein a portion of an end of the third portion opposite to the second portion is spaced apart from an edge of the semiconductor substrate.

A semiconductor chip comprising:

• a semiconductor substrate comprising a die region in which a plurality of chip pads are arranged and a residual scribe lane at least partially surrounding a periphery of a die edge of the die region,
• a passivation layer at least partially covering a portion above the semiconductor substrate;
• and
• a cover protection layer at least partially covering a portion of the passivation layer,
• wherein the residual scribe lane comprises a plurality of crossing regions, which are a portion adjacent to each corner of the semiconductor substrate, and a test region, which is a portion wherein a plurality of residual test pads are disposed between the plurality of crossing regions, and
• wherein the cover protection layer comprises:
• a cover central portion at least partially covering the area inside of the die edge,
• a cover peripheral portion having a constant width from the die edge and surrounding the cover central portion and covering a portion of the residual scribe lane,
• a corner protection layer in contact with a portion of an edge of the semiconductor substrate in the crossing region, and
• an extending protection layer extending from the corner protection layer along the residual scribe lane and in contact with the cover peripheral portion in the crossing region.