Fin critical dimension loading optimization

An integrated circuit device comprising:

• a first fin-like field effect transistor (FinFET) having a multi-fin structure disposed over a substrate, wherein the multi-fin structure includes intra-fins disposed between a first inter-fin and a second inter-fin;
• wherein the first inter-fin, the second inter-fin, and the intra-fins are completely disposed within one region of the integrated circuit device;
• wherein the first inter-fin and the second inter-fin are edge fins of the multi-fin structure of the first FinFET having an inter-fin width and the intra-fins are center fins of the multi-fin structure of the first FinFET having an intra-fin width, wherein the inter-fin width is greater than the intra-fin width;
• wherein the first inter-fin has a first inter-fin adjacent fin pitch that is a sum of a first right fin pitch and a first left fin pitch, wherein the first right fin pitch is between the first inter-fin and a directly adjacent respective intra-fin positioned right of the first inter-fin and the first left fin pitch is between the first inter-fin and a directly adjacent fin of a second FinFET positioned left of the first inter-fin;
• wherein the second inter-fin has a second inter-fin adjacent fin pitch that is a sum of a second right fin pitch and a second left fin pitch, wherein the second right fin pitch is between the second inter-fin and a directly adjacent fin of a third FinFET positioned right of the second inter-fin and the second left fin pitch is between the second inter-fin and a directly adjacent respective intra-fin positioned left of the second inter-fin;
• wherein the second inter-fin adjacent fin pitch and the first inter-fin adjacent fin pitch are greater than or equal to three times a minimum fin pitch;
• and
• wherein the intra-fins have an intra-fin adjacent fin pitch that is less than or equal to two times the minimum fin pitch.

A method comprising:

• forming a first multi-fin structure of a first fin-like field effect transistor (FinFET) completely within a core region, wherein the first multi-fin structure has first fins having a first fin width and each of the first fins has a first portion disposed between second portions;
• forming a second multi-fin structure of a second FinFET completely within a peripheral region, wherein the second multi-fin structure has second fins having a second fin width and each of the second fins has a third portion disposed between fourth portions, and further wherein the first fin width is greater than the second fin width and a number of the first fins is less than a number of the second fins;
• and
• forming a first gate structure over and wrapping the first portion of each of the first fins of the first multi-fin structure and a second gate structure over and wrapping the third portion of each of the second fins of the second multi-fin structure.