Low thermal budget top source and drain region formation for vertical transistors

A method of forming a semiconductor device comprising:

• forming a plurality of vertically orientated channel regions each present in a semiconductor fin structure that is present on a supporting substrate;
• forming a gate structure adjacent sidewalls of the semiconductor fin and over source/drain regions;
• forming a first spacer between teh source/drain regions and the gate structure;
• forming a second spacer over the gate structure, such that the first and second spacers are on opposed ends of the gate structure;
• depositing a doped amorphous semiconductor material on an upper surface of each of said semiconductor fin structure for the plurality of vertically orientated channel regions that are opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate;
• and
• recrystallizing the doped amorphous semiconductor material with an anneal to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure, wherein the doped polycrystalline source and/or drain region has a planar upper surface and provides a merging structure between adjacent fin structures that provide the plurality of vertically orientated channel regions.