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AssigneeTessera, Inc.
InventorsChristopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
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A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
A semiconductor structure for integrating a fully-aligned via (FAV) with airgaps, the semiconductor structure comprising:
A semiconductor structure for integrating a fully-aligned via (FAV) with airgaps, the semiconductor structure comprising:
Dependencies are inferred from the claim text.