3D semiconductor device and structure

A 3D semiconductor device, the device comprising:

• a first level comprising:
• (i) a first single crystal layer
• wherein said first single crystal layer includes a plurality of first transistors and (ii) a first metal layer,
• wherein said first metal layer comprises interconnections between said first transistors, and
• wherein at least a portion of said first transistors form a plurality of logic gates;
• a second level comprising a plurality of second transistors,
• wherein said second transistors are atop said first metal layer;
• a second metal layer overlaying, at least in part said second transistors;
• and
• Input/Output pad structures to provide connections to external devices,
• wherein said second transistors are aligned to said first transistors with less than 40 nm misalignment,
• wherein said first single crystal layer comprises an electrostatic discharge (“ESD”) structure connected to at least one of said Input/Output pad structures,
• wherein at least one of said second transistors comprises a source, a drain, and a transistor channel,
• wherein said source, said drain and said transistor channel comprise a same dopant type,
• wherein a memory cell comprises at least one of said second transistors,
• wherein said local power grid is disposed underneath said second level,
• wherein said global power grid is connected to said local power grid by a plurality of vias.

A 3D semiconductor device, the device comprising:

• a first level comprising:
• (i) a first single crystal layer,
• wherein said first single crystal layer includes a plurality of first transistors and iii) a first metal layer,
• wherein said first metal layer comprises interconnections between said first transistors, and
• wherein at least a portion of said first transistors form a plurality of logic gates;
• a second level comprising a plurality of second transistors,
• wherein said second transistors are atop said first metal layer;
• a second metal layer overlaying, at least in part said second transistors;
• and
• Input/Output pad structures to provide connections to external devices,
• wherein said second transistors are aligned with less than 40 nm misalignment to said first transistors, and
• wherein said first single crystal layer comprises an electrostatic discharge (“ESD”) structure connected to at least one of said Input/Output pad structures,
• wherein at least one of said second transistors comprises a source, a drain, and a transistor channel,
• wherein said source, said drain and said transistor channel comprise a same dopant type, and
• wherein said second metal layer has a current carrying capacity at least twice a current carrying capacity than said first metal layer.