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US 10,651,051 B2Granted
Embedded semiconductive chips in reconstituted wafers, and systems containing same
AssigneeIntel Corporation
InventorsRobert L. Sankman, John S. Guzek
Life of this patent
Estimating the term…
Abstract
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
Claims10
A microelectronic package comprising:
- an encapsulation mass with a terminal-exposing surface and a base surface disposed parallel planar to the terminal-exposing surface;
- a first semiconductor die and a second semiconductor die embedded in the encapsulation mass, wherein each of the first and second semiconductor dice has an active surface and a backside surface, wherein the backside surface of at least one of the first semiconductor die and the second semiconductor die is coplanar with the encapsulation mass base surface, and wherein the first semiconductor die comprises a processor die and the second semiconductor die comprises a memory die;
- a terminal on the first semiconductor die, wherein the terminal has a surface that is coplanar with the encapsulation mass terminal-exposing surface;
- a terminal on the second semiconductor die, wherein the terminal has a surface that is coplanar with the encapsulation mass terminal-exposing surface;
- at least one dielectric layer and at least one metallization over the terminals of each of the processor die and the memory die and the terminal-exposing surface, wherein the at least one dielectric and at least one metallization over the terminals, couples the processor die and the memory die.
2 more elements
A microelectronic package comprising:
- an encapsulation mass with a terminal-exposing surface and a base surface disposed parallel planar to the terminal-exposing surface;
- a first semiconductor die and a second semiconductor die embedded in the encapsulation mass, wherein each of the first and second semiconductor dice has an active surface and a backside surface, wherein the backside surface of at least one of the first semiconductor die and the second semiconductor die is coplanar with the encapsulation mass base surface, and wherein the first semiconductor die comprises a processor die and the second semiconductor die comprises a memory die;
- a terminal on the first semiconductor die, wherein the terminal has a surface that is coplanar with the encapsulation mass terminal-exposing surface;
- a terminal on the second semiconductor die, wherein the terminal has a surface that is coplanar with the encapsulation mass terminal-exposing surface;
- at least one dielectric layer and at least one metallization over the terminals of each of the processor die and the memory die and the terminal-exposing surface, wherein the at least one dielectric and at least one metallization over the terminals, couples the processor die and the memory die;
- a bond pad coupled to the at least one metallization;
- a microelectronic die flip-chip first device coupled to the bond pad;
- and
- wherein the terminal for one of the processor die and the memory die, is taller than for the other of the processor die and memory die.
6 more elements
Dependencies are inferred from the claim text.