Polysilicon gate formation in CMOS transistors
AssigneeTexas Instruments Incorporated
InventorsPushpa Mahalingam, Umamaheswari Aghoram
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Abstract
A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.
Claims22
A method of forming a semiconductor device, comprising:
- forming source regions and drain regions in a semiconductor wafer;
- forming a gate electrode over said semiconductor substrate and between said source and drain regions;
- forming a gate dielectric layer between said gate electrode and said wafer,
- wherein said gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer and a second semiconductor gate electrode layer deposited on said first semiconductor gate electrode layer, the second semiconductor gate electrode layer having a thickness about seven times a thickness of the first semiconductor gate electrode layer, and
- annealing said first and second semiconductor gate electrode layers in a wafer-level process;
- and
- said annealing results in a single homogenous polysilicon layer.
A method of forming a semiconductor device, comprising:
- providing a semiconductor wafer;
- locating source/drain regions within the semiconductor wafer;
- forming a gate oxide layer over said wafer between said source/drain regions;
- forming on said gate oxide layer a first semiconductor layer having a first thickness;
- and
- forming on said first semiconductor layer a second semiconductor layer having a second thickness about seven times the first thickness;
- and
- annealing said first and second semiconductor layers in a wafer-level process to produce a single homogenous polycrystalline layer,
- wherein said homogenous polycrystalline layer has a mean grain size of 50 nm and a grain size standard deviation of 10 nm.
A method of forming a semiconductor device, comprising:
- providing a semiconductor wafer;
- locating source/drain regions within the semiconductor wafer;
- forming a gate oxide layer over said wafer between said source/drain regions;
- forming on said gate oxide layer a first semiconductor layer at a first growth rate;
- forming on said first semiconductor layer a second semiconductor layer at a second greater growth rate;
- and
- annealing said first and second semiconductor layers in a wafer-level process to produce a single homogenous polycrystalline layer,
- wherein said homogenous polycrystalline layer has a mean grain size of about 50 nm and a grain size standard deviation of about 10 nm.
Dependencies are inferred from the claim text.