Memory bypass function for a memory
AssigneeSynopsys, Inc.
InventorsJohn Edward Barth, Jr., Kevin W. Gorman, Harold Pilo
Life of this patent
Estimating the term…
Abstract
A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.
Claims21
A memory bypass circuit for a memory device, comprising:
- a word line disable circuit;
- and
- a read and write activation circuit;
- wherein the word line disable circuit is coupled to a word line of the memory device, and
- wherein the read and write activation circuit is coupled to the memory device for concurrent activation of writing and reading functions of the memory device during a testing mode.
A method for providing a write through function for a memory device, comprising:
- disabling word line activation;
- concurrently activating read and write functions of the memory device;
- generating an internal clock signal for the concurrently activated read and write functions;
- and
- providing known data to the memory device for writing to bit lines of the memory device during a testing mode.
A memory system, the system comprising:
- a memory;
- and
- a memory bypass circuit, wherein the memory bypass circuit comprises:
- a word line disable circuit;
- a read and write activation circuit;
- a internal clock generator;
- and
- a write data input circuit,
- wherein the word line disable circuit is coupled to a word line of the memory device,
- wherein the read and write activation circuit is coupled to the memory device for concurrent activation of writing and reading functions of the memory device during a testing mode,
- wherein the internal clock generator is coupled to the word line disable circuit and the read/write activation circuit, and
- wherein the write data input circuit is coupled to a write driver of the memory device for providing test data.
Dependencies are inferred from the claim text.