Stacked type semiconductor memory device and method for reading the same

A semiconductor memory device, comprising:

• a plurality of interconnects extending in a first direction and being arranged along a second direction and a third direction, the second direction crossing the first direction, the third direction crossing a plane including the first direction and the second direction;
• a plurality of semiconductor members extending in the second direction and being disposed between two interconnects of the plurality of interconnects adjacent to each other in the third direction;
• a charge storage member disposed between one of the semiconductor members and a first interconnect of the plurality of interconnects;
• and
• a drive circuit configured to, when evaluating an amount of charge stored in the charge storage member,
• apply a voltage between two end portions of the one of the semiconductor members,
• apply a potential for evaluating the amount of charge to the first interconnect,
• apply a first potential to a second interconnect of the plurality of interconnects,
• apply a second potential to a third interconnect of the plurality of interconnects,
• apply the first potential to at least one of a plurality of fourth interconnects of the plurality of interconnects,
• apply the second potential to a fifth interconnect of the plurality of interconnects, and
• apply the second potential to a sixth interconnect of the plurality of interconnects,
• the one of the semiconductor members being settable to a conducting state by the first potential,
• the second interconnect being arranged in the second direction when viewed from the first interconnect,
• the third interconnect being arranged in the third direction when viewed from the first interconnect,
• the one of the semiconductor members being interposed between the third interconnect and the first interconnect,
• the one of the semiconductor members being settable to a nonconducting state by the second potential,
• the plurality of fourth interconnects being arranged in the second direction when viewed from the third interconnect and being nonadjacent to the third interconnect in the second direction,
• the fifth interconnect being adjacent to the third interconnect in the second direction, and
• the sixth interconnect being adjacent to the fifth interconnect in the second direction.

A method for driving a semiconductor memory device, the device including a first NAND string and a second NAND string sharing a channel and being connected in parallel between a first interconnect and a second interconnect, the first and second NAND strings each including a plurality of memory cell transistors connected in series, the method comprising, when reading a value from a first memory cell transistor of the plurality of memory cell transistors belonging to the first NAND string:

• applying a first potential to a gate of a second memory cell transistor of the plurality of memory cell transistors belonging to the first NAND string other than the first memory cell transistor;
• applying a second potential to a gate of a third memory cell transistor of the plurality of memory cell transistors belonging to the second NAND string, the third memory cell transistor opposing the first memory cell transistor, an absolute value of a potential difference between the second potential and a potential of the first interconnect being less than an absolute value of a potential difference between the first potential and the potential of the first interconnect;
• applying the first potential to a gate of at least one of fourth memory cell transistors of the plurality of memory cell transistors belonging to the second NAND string, the fourth memory cell transistor opposing the second memory cell transistor and being nonadjacent to the third memory cell transistor;
• applying the second potential to a gate of a fifth memory cell transistor of the plurality of memory cell transistors belonging to the second NAND string, the fifth memory cell transistor being adjacent to the third memory cell transistor;
• applying the second potential to a gate of a sixth memory cell transistor of the plurality of memory cell transistors belonging to the second NAND string, the sixth memory cell transistor being adjacent to the fifth memory cell transistor;
• and
• sweeping a gate potential of the first memory cell transistor between the second potential and the first potential.